In the related art, a volatile memory (RAM) such as a dynamic random access memory (DRAM) is known as a storage device. DRAMs are required to have high performance of an arithmetic unit (hereinafter referred to as a logic chip) and a large capacity capable of withstanding an increase in amount of data. Therefore, the capacity has been increased by miniaturizing a memory (memory cell array, memory chip) and increasing the number of cells in a plane. On the other hand, this type of increase in capacity has reached its limit due to the weakness to noise caused by the miniaturization, the increase in die area, and the like.
Therefore, in recent years, a technology has been developed that realizes a large capacity by laminating a plurality of planar memories to form a three-dimensional (3D) structure. In addition, there has been proposed a semiconductor module that reduces an installation area of the logic chip and the RAM by overlapping the logic chip and RAM (see, for example, Patent Documents 1 to 4).    Patent Document 1: Japanese Unexamined Patent Application (Translation of PCT Application), Publication No. 2014-512691    Patent Document 2: Japanese Unexamined Patent Application (Translation of PCT Application), Publication No. 2013-501380    Patent Document 3: Japanese Unexamined Patent Application, Publication No. 2010-232659    Patent Document 4: Japanese Unexamined Patent Application, Publication No. 2010-80802